Verilog Digital System Design: Register transfer level synthesis, testbench and verification (Record no. 2175)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 01282nam a22002297a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190523152303.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 190523b ||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978-0-07-025221-9 |
| 028 ## - PUBLISHER NUMBER | |
| Source | Allied Informatics, Jaipur |
| Bill Number | 6195 |
| Bill Date | 20/05/2019 |
| Purchase Year | 2019-20 |
| 040 ## - CATALOGING SOURCE | |
| Original cataloging agency | BSDU |
| Language of cataloging | English |
| Transcribing agency | BSDU |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 |
| Item number | NAV |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Navabi, Zainalabedin |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog Digital System Design: Register transfer level synthesis, testbench and verification |
| 250 ## - EDITION STATEMENT | |
| Remainder of edition statement | 2nd |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Mcgraw Hill Education (India) Pvt. Ltd. |
| Date of publication, distribution, etc. | 2008; c2006 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 384 |
| 500 ## - GENERAL NOTE | |
| General note | This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library. |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE | |
| Bibliography, etc. note | Contents: 1. Digital System Design Automation with Verilog 2. Register Transfer Level Design with Verilog 3. Verilog Language Concepts 4. Combinational Circuit Description 5. Sequential Circuit Description 6.Component Test and Verification 7. Detailed Modeling 8. RT Level Design and Test Appendix Index |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electronics |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | |
| Koha item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent Location | Current Location | Shelving location | Date acquired | Cost, normal purchase price | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | General Stacks | 2019-05-23 | 695.00 | 621.392 NAV | 017769 | 2020-02-12 | 695.00 | 2019-05-23 | Books | |||||
| Not For Loan | BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | General Stacks | 2019-05-23 | 695.00 | 621.392 NAV | CD848 | 2019-05-23 | 695.00 | 2019-05-23 | CDs & DVDs |