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Introduction to Switching Theory & Logical Design (Record no. 571)

000 -LEADER
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001 - CONTROL NUMBER
control field 0002168
003 - CONTROL NUMBER IDENTIFIER
control field OSt
005 - DATE AND TIME OF LATEST TRANSACTION
control field 20190318134034.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
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020 ## - INTERNATIONAL STANDARD BOOK NUMBER
International Standard Book Number 9788126520312
028 ## - PUBLISHER NUMBER
Qualifying information 2016
Source Allied Informatics, Jaipur
040 ## - CATALOGING SOURCE
Language of cataloging English
Original cataloging agency BSDU
Transcribing agency BSDU
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number 621.381 527
Item number HIL
100 ## - MAIN ENTRY--PERSONAL NAME
Personal name Hill, Fredrick J
245 #0 - TITLE STATEMENT
Title Introduction to Switching Theory & Logical Design
250 ## - EDITION STATEMENT
Edition statement 3rd
260 ## - PUBLICATION, DISTRIBUTION, ETC.
Name of publisher, distributor, etc. Wiley India Pvt. Ltd. India
Place of publication, distribution, etc. New Delhi
Date of publication, distribution, etc. 2011,c1981
300 ## - PHYSICAL DESCRIPTION
Extent 617
500 ## - GENERAL NOTE
General note In this edition, author provides revised and updated information on AHPL. Two programs namely a functional level simulator and a hardware compiler have been added in this textbook to support AHPL. The language used in Chapters 11 and 12 to describe hardware is completely consistent with the AHPL of the previous edition. Chapter 9 has been expanded to provide more through coverage of various types of flip-flops. Chapter 3 and 4 provide the basic logical and algebraic basis for switching theory. Chapter 5 has been rewritten to reflect recent innovations in digital circuit design. The important topic of programmed logic arrays (PLAs) has been added to Chapter 8. The chapter on level mode analysis and synthesis has been improved and extended to include the edge-triggered D flip-flop.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc. note Contents
Introduction

· Number Systems

· Truth Functions

· Boolean Algebra

· Switching Devices

· Minimization of Boolean Functions

· Tabular Minimization and Multiple-Output Circuits

· Special Realization and Codes

· Introduction to Sequential Circuits

· Synthesis of Clock-Mode Sequential Circuits

· Clock-Control and Pulse-Mode Circuits

· Logical Design Using MSI and LSI Parts

· Incompletely Specified Sequential Circuits

· Level-Mode Sequential Circuits

· A Second Look at Flip-Flops and Timings

· Combinational Functions with Special Properties

Appendix A

Selection of Minimal Closed Covers

Bibliography

Appendix B

Relay Circuits

Index
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical term or geographic name entry element Electronics
700 ## - ADDED ENTRY--PERSONAL NAME
Personal name Peterson, Gerald R
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Source of classification or shelving scheme
Koha item type Books
Holdings
Withdrawn status Lost status Source of classification or shelving scheme Damaged status Not for loan Permanent Location Current Location Date acquired Cost, normal purchase price Full call number Barcode Date last seen Cost, replacement price Price effective from Koha item type Collection code
          BSDU Knowledge Resource Center, Jaipur BSDU Knowledge Resource Center, Jaipur 2016-12-11 599.00 621.381 527 HIL 002168 2020-02-12 599.00 2017-06-02 Books  
          BSDU Knowledge Resource Center, Jaipur BSDU Knowledge Resource Center, Jaipur 2016-12-11 599.00 621.381 527 HIL 002169 2020-02-12 599.00 2017-06-02 Books  
        Not For Loan BSDU Knowledge Resource Center, Jaipur BSDU Knowledge Resource Center, Jaipur 2016-12-11 599.00 621.381 527 HIL 002170 2020-02-12 599.00 2017-06-02 Books Not for Loan

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