VLSI Digital Signal Processing Systems : Design and Implementation
By: Parhi, Keshab K.
Material type: BookPublisher: New Delhi Wiley India Pvt. Ltd. India 2012,c1999Description: 784.ISBN: 9788126510986.Subject(s): ElectronicsDDC classification: 621.395Item type | Current location | Collection | Call number | Status | Date due | Barcode |
---|---|---|---|---|---|---|
Books | BSDU Knowledge Resource Center, Jaipur | 621.395 PAR (Browse shelf) | Available | 001377 | ||
Books | BSDU Knowledge Resource Center, Jaipur | 621.395 PAR (Browse shelf) | Available | 001378 | ||
Books | BSDU Knowledge Resource Center, Jaipur | Not for Loan | 621.395 PAR (Browse shelf) | Not For Loan | 001379 | |
Books | BSDU Knowledge Resource Center, Jaipur | 621.395 PAR (Browse shelf) | Available | 001380 |
Browsing BSDU Knowledge Resource Center, Jaipur Shelves , Collection code: Not for Loan Close shelf browser
621.395 MAN Digital Design with an Introduction to the Verilog HDL | 621.395 MAN Logic and Computer Design Fundamentals | 621.395 MAN Digital Logic and Computer Design | 621.395 PAR VLSI Digital Signal Processing Systems : Design and Implementation | 621.395 PHA Digital Logic Design and Principles | 621.395 ROY Low-Power CMOS VLSI Circuit Design | 621.395 UYE Introduction to VLSI Circuits and Systems |
This book complements the other Digital Signaling Processing books in our list, which include an introductory treatment (Marven), a comprehensive handbook (Mitra), a professional reference (Kaloupsidis), and others which pertain to a specific topic such as noise control. This graduate level textbook will fill an important niche in a rapidly expanding market.
Contents
· Introduction to Digital Signal Processing Systems
· Iteration Bound
· Pipelining and Parallel Processing
· Retiming
· Unfolding
· Folding
· Systolic Architecture Design
· Fast Convolution
· Algorithmic Strength Reduction in Filters and Transforms
· Pipelined and Parallel Recursive and Adaptive Filters
· Scaling and Round off Noise
· Digital Lattice Filter Structures
· Bit-Level Arithmetic Architectures
· Redundant Arithmetic
· Numerical Strength Reduction
· Synchronous
There are no comments for this item.