VHDL Primer
By: Bhaskar, J.
Material type:
BookPublisher: New Delhi Pearson Education 2016Edition: 3rd.Description: 395.ISBN: 9789332557161.Subject(s): ElectronicsDDC classification: 621.392
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| 621.392 BHA VHDL Primer | 621.392 BHA VHDL Primer | 621.392 BHA VHDL Primer | 621.392 BHA VHDL Primer | 621.392 BHA VHDL Primer | 621.392 KAU VHDL: Basics to Programming | 621.392 NAV Verilog Digital System Design: Register transfer level synthesis, testbench and verification |
This book introduces the VHDL language to the reader at the beginner's level. It presents a subset of VHDL consisting of commonly used features that make it both simple and easy to use. The extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more.
Table of Content
Chapter 1 Introduction
Chapter 2 A Tutorial
Chapter 3 Basic Language Elements
Chapter 4 Behavioral Modeling
Chapter 5 Dataflow Modeling
Chapter 6 Structural Modeling
Chapter 7 Generics and Configurations
Chapter 8 Subprograms and Overloading
Chapter 9 Packages and Libraries
Chapter 10 Advanced Features
Chapter 11 Model Simulation
Chapter 12 Hardware Modeling Examples
Appendix A Predefined Environment
Appendix B Syntax Reference
Appendix C A Package Example
Appendix D Summary of Changes
Appendix E The STD_LOGIC_1164 Package
Appendix F An Utility Package
Appendix G Solved Questions
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