Bhaskar, J. <br/><br/>
VHDL Primer 

 - 3rd 
 - New Delhi  Pearson Education  2016 
 - 395 
<br/><br/> This book introduces the VHDL language to the reader at the beginner's level. It presents a subset of VHDL consisting of commonly used features that make it both simple and easy to use. The extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. 
<br/><br/>Table of Content<br/>Chapter 1 Introduction<br/><br/>Chapter 2 A Tutorial<br/><br/>Chapter 3 Basic Language Elements<br/><br/>Chapter 4 Behavioral Modeling<br/><br/>Chapter 5 Dataflow Modeling<br/><br/>Chapter 6 Structural Modeling<br/><br/>Chapter 7 Generics and Configurations<br/><br/>Chapter 8 Subprograms and Overloading<br/><br/>Chapter 9 Packages and Libraries<br/><br/>Chapter 10 Advanced Features<br/><br/>Chapter 11 Model Simulation<br/><br/>Chapter 12 Hardware Modeling Examples<br/><br/>Appendix A Predefined Environment<br/><br/>Appendix B Syntax Reference<br/><br/>Appendix C A Package Example<br/><br/>Appendix D Summary of Changes<br/><br/>Appendix E The STD_LOGIC_1164 Package<br/><br/>Appendix F An Utility Package<br/><br/>Appendix G Solved Questions 
<br/><br/><label>ISBN: </label>9789332557161 
<br/><br/><label>Publisher. No.: </label> Allied Informatics, Jaipur 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electronics
<br/><br/><label>Dewey Class. No.: </label>621.392   / BHA