Singar, Sumitra <br/><br/>
Low Power Fault Tolerant Latches and Flip-flops: Design and performance analysis 

 - Mauritius  Lambert Academic Publishing  2018 
 - 128 
<br/><br/> This book focus on review, study and design of fault tolerant circuits to reduce circuit-level faults and protect a circuit from faults. In this book eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure. 
<br/><br/>Contents<br/>Introduction<br/>Existing Fault Tolerant Latches and Flip-Flops<br/>Fault Free D-Latch Configurations<br/>Robust Fault Resistant D-Latch<br/>Glitch Free Novel Det Flip-Flop<br/>Near & Super Threshold Regions Impact on Power and Delay<br/>Conclusions 
<br/><br/><label>ISBN: </label>978-613-9-45302-3 
<br/><br/><label>Publisher. No.: </label> Lambert Academic Publishing 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Electrical
<br/><br/><label>Dewey Class. No.: </label>621.3  / SIN