000			01282nam a22002297a 4500
999			_c2175 _d2175
003			OSt
005			20190523152303.0
008			190523b ||||| |||| 00| 0 eng d
020			_a978-0-07-025221-9
028			_bAllied Informatics, Jaipur _c6195 _d20/05/2019 _q2019-20
040			_aBSDU _bEnglish _cBSDU
082			_a621.392 _bNAV
100			_aNavabi, Zainalabedin
245			_aVerilog Digital System Design: Register transfer level synthesis, testbench and verification
250			_b2nd
260			_aNew Delhi _bMcgraw Hill Education (India) Pvt. Ltd. _c2008; c2006
300			_a384
500			_aThis rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.
504			_aContents: 1. Digital System Design Automation with Verilog 2. Register Transfer Level Design with Verilog 3. Verilog Language Concepts 4. Combinational Circuit Description 5. Sequential Circuit Description 6.Component Test and Verification 7. Detailed Modeling 8. RT Level Design and Test Appendix Index
650			_aElectronics
942			_2ddc _cBK