000			02158nam a2200253Ia 4500
999			_c571 _d571
001			0002168
003			OSt
005			20190318134034.0
008			170602s9999 xx 000 0 und d
020			_a9788126520312
028			_q2016 _bAllied Informatics, Jaipur
040			_bEnglish _aBSDU _cBSDU
082			_a621.381 527 _bHIL
100			_aHill, Fredrick J
245		0	_aIntroduction to Switching Theory & Logical Design
250			_a3rd
260			_bWiley India Pvt. Ltd. India _a New Delhi _c2011,c1981
300			_a617
500			_aIn this edition, author provides revised and updated information on AHPL. Two programs namely a functional level simulator and a hardware compiler have been added in this textbook to support AHPL. The language used in Chapters 11 and 12 to describe hardware is completely consistent with the AHPL of the previous edition. Chapter 9 has been expanded to provide more through coverage of various types of flip-flops. Chapter 3 and 4 provide the basic logical and algebraic basis for switching theory. Chapter 5 has been rewritten to reflect recent innovations in digital circuit design. The important topic of programmed logic arrays (PLAs) has been added to Chapter 8. The chapter on level mode analysis and synthesis has been improved and extended to include the edge-triggered D flip-flop.
504			_aContents Introduction · Number Systems · Truth Functions · Boolean Algebra · Switching Devices · Minimization of Boolean Functions · Tabular Minimization and Multiple-Output Circuits · Special Realization and Codes · Introduction to Sequential Circuits · Synthesis of Clock-Mode Sequential Circuits · Clock-Control and Pulse-Mode Circuits · Logical Design Using MSI and LSI Parts · Incompletely Specified Sequential Circuits · Level-Mode Sequential Circuits · A Second Look at Flip-Flops and Timings · Combinational Functions with Special Properties Appendix A Selection of Minimal Closed Covers Bibliography Appendix B Relay Circuits Index
650			_aElectronics
700			_a Peterson, Gerald R
942			_2ddc _cBK