Padmanabhan, T R
Design Through Verilog HDL - New Delhi Wiley India Pvt. Ltd. India 2015,c2004 - 455
If you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog.
Contents
Preface
Acknowledgements
· Introduction to VLSI Design
· Introduction to Verilog
· Language Constructs and Conventions in Verilog
· Gate Level Modeling - 1
· Gate Level Modeling - 2
· Modeling at Data Flow Level
· Behavioral Modeling - 1
· Behavioral Modeling II
· Functions, Tasks, and User-Defined Primitives
· Switch Level Modeling 305
· System Tasks, Functions, and Compiler Directives 339
· Queues, PLAS, and FSMS
Appendix A (Keywords and Their Significance)
Appendix B (Truth Tables of Gates and Switches)
References
Index
9788126519316
Allied Informatics, Jaipur
Electronics
621.392 / PAD
Design Through Verilog HDL - New Delhi Wiley India Pvt. Ltd. India 2015,c2004 - 455
If you aspire to master Verilog language and become a competent EDA professional, this book is for you. It fills the need for an elaborate construct in Verilog, and clarifies their implications, illustrating their need and utility. This is especially true fo the latest IEEE Standard 1364 for Verilog.
Contents
Preface
Acknowledgements
· Introduction to VLSI Design
· Introduction to Verilog
· Language Constructs and Conventions in Verilog
· Gate Level Modeling - 1
· Gate Level Modeling - 2
· Modeling at Data Flow Level
· Behavioral Modeling - 1
· Behavioral Modeling II
· Functions, Tasks, and User-Defined Primitives
· Switch Level Modeling 305
· System Tasks, Functions, and Compiler Directives 339
· Queues, PLAS, and FSMS
Appendix A (Keywords and Their Significance)
Appendix B (Truth Tables of Gates and Switches)
References
Index
9788126519316
Allied Informatics, Jaipur
Electronics
621.392 / PAD