Verilog Digital Computer Design: Algorithms into hardware (Record no. 2211)
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000 -LEADER | |
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fixed length control field | 02517nam a22002177a 4500 |
003 - CONTROL NUMBER IDENTIFIER | |
control field | OSt |
005 - DATE AND TIME OF LATEST TRANSACTION | |
control field | 20190530102059.0 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
fixed length control field | 190530b ||||| |||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
International Standard Book Number | 978-81-317-3371-4 |
028 ## - PUBLISHER NUMBER | |
Source | Allied Informatics, Jaipur |
Bill Number | 6218 |
Bill Date | 29/05/2019 |
Purchase Year | 2019-20 |
040 ## - CATALOGING SOURCE | |
Original cataloging agency | BSDU |
Language of cataloging | English |
Transcribing agency | BSDU |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
Classification number | 621.392 |
Item number | ARN |
100 ## - MAIN ENTRY--PERSONAL NAME | |
Personal name | Arnold, Mark Gordon |
245 ## - TITLE STATEMENT | |
Title | Verilog Digital Computer Design: Algorithms into hardware |
260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
Place of publication, distribution, etc. | New Delhi |
Name of publisher, distributor, etc. | Pearson Education |
Date of publication, distribution, etc. | 2010 |
300 ## - PHYSICAL DESCRIPTION | |
Extent | 602 |
500 ## - GENERAL NOTE | |
General note | Written by the co-developer of the Verilog Implicit To One hot (VITO) preprocessor, this text introduces the industry standard Verilog Hardware Description Language as a new way to explore enduring concepts in digital and computer design, such as pipelining. It shows how Verilog simulation is a tool for uncovering bugs prior to hardware fabrication, and how Verilog synthesis is a tool for automatically converting source code into hardware. Ideal for designers new to Verilog, it features a consistent design framework using ASM charts, and contains many realistic, practical examples. For Sale in Indian subcontinent only Understand the fundamental goals, structure, and behavior of Verilog; Discover how to use ASMs as the "master plan" for digital design; Walk through the three stages of Verilog design: behavioral, mixed, and structural; Learn Verilog simulation techniques for Mealy machines and bottom-testing loops; Use Verilog simulation techniques to model propagation delay; Leverage special-purpose design techniques to build general-purpose processors; Build a CPU from a ready-to-synthesize programmable logic example. Verilog Digital Computer Design: Algorithms to Hardware is more than a great guide to Verilog: it's a primer on the enduring concepts of computer design that will apply no matter which tools you choose. |
504 ## - BIBLIOGRAPHY, ETC. NOTE | |
Bibliography, etc. note | Contents Why Verilog Computer Design? Designing ASMs Verilog Hardware Description Language Three Stages For Verilog Design Advanced ASM Techniques Designing For Speed and Cost One Hot Designs General- Purpose Computers Pipelined General-Purpose Processor Risc Processors Synthesis Appendices A Machine and Assembly Language B PDP-8 Commands C Combinational Logic Building Blocks D Sequential Logic Building Blocks E Tri-State Devices F Tools and Resources G Arm Instructions H Another View on Non-Blocking Assignment I Glossary J Limitation on Mealy with Implicit Style |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
Topical term or geographic name entry element | Electrical |
942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
Source of classification or shelving scheme | |
Koha item type | Books |
Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection code | Permanent Location | Current Location | Date acquired | Cost, normal purchase price | Full call number | Barcode | Date last seen | Cost, replacement price | Price effective from | Koha item type |
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Not For Loan | Reference | BSDU Knowledge Resource Center, Jaipur | BSDU Knowledge Resource Center, Jaipur | 2019-05-30 | 1295.00 | 621.392 ARN | 017776 | 2020-02-12 | 1295.00 | 2019-05-30 | Books |